KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
High Speed Digital Blocks
NB7V52MMNG Datasheet(PDF) - ON Semiconductor
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:6880895
RTD-based High Speed and Low Power Integrated Circuits RTD-based High Speed and Low Power Integrated Circuits
PDF) Resonant Tunneling Diode/HBT D-Flip Flop ICs Using Current Mode Logic-Type Monostable-Bistable Transition Logic Element with Complementary Outputs | Taeho Kim - Academia.edu
NB7V52M Flip-Flop Datasheet pdf - D Flip-Flop. Equivalent, Catalog
adding reset function to D Flip FLOP | Forum for Electronics
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
Part 01: Proposal and Overview. Dual Modulus Prescaler Using Current Mode Logic Goals 2.5 GHz Operation 8/9 Dual Modulus 0.18uM BSIM 3 Model. - ppt download
adding reset function to D Flip FLOP | Forum for Electronics
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
digital logic - D flip flop with asynchronous reset circuit design - Electrical Engineering Stack Exchange
adding reset function to D Flip FLOP | Forum for Electronics
adding reset function to D Flip FLOP | Forum for Electronics
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
A 2-GHz, Low Noise, Low Power CMOS Frequency Synthesizer with an LC-tuned VCO for Wireless Communications
![PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/a9f1b39596e7f08405b62eebe623914a1e5c78d1/2-Figure2-1.png "PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar")
PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar
MC74VHC74 datasheet - Dual D Flip-Flop with Set and Reset. The MC74VHC74
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
high frequency D flip flop for phase detector - RF Design - Cadence Technology Forums - Cadence Community
Edge Triggered D Flip-Flop with Asynchronous Set and Reset Tutorial
